/*
utf-8
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50MHZ时钟转1kHZ时钟程序
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由刘丙旭出品
遵循署名-非商业性使用-相同方式共享 4.0 国际协议 (CC BY-NC-SA 4.0)
详情访问https://creativecommons.org/licenses/by-nc-sa/4.0/deed.zh
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*/
module clk_50MHz_1kHz(clk_50MHz,clk_1kHz);
	input clk_50MHz;
	output clk_1kHz;
	reg clk_1kHz = 0;
	
	reg[17:0] div = 0;
	
	always @(posedge clk_50MHz)
	begin
		if(div == 24999)
			begin div <= 0; clk_1kHz <= ~clk_1kHz; end
		else
			div <= div + 1;
	end

endmodule
